Embodiments of the inventive subject matter generally relate to the field of hardware testing and, more particularly, to an integrated functional testing mechanism for integrated circuits.
To ensure the validity of the operations of various components (e.g., cache memories, communication interfaces, etc.) of a system on a chip (SoC), streams of binary signals at nodes that are to be tested (“test nodes”) can be characterized during test periods. For example, changes in binary logic levels of data signals at a test node may be counted during a test period and may be compared to an expected number of data transitions for the same test node. As another example, signature analysis can be implemented on the SoC. Using signature analysis, a data word that is indicative of a digital signal generated at a test node of the SoC during a test period can be determined. The data word generated at the test node can be compared against expected data words associated with the test node to determine the presence of errors in the SoC.